1. Field of Invention
This invention relates to integrated circuit packaging, and more particularly, to a packaging layout that provides high density routing of signal lines as differential pairs with approximately equal trace lengths and as a pair of signal conductor planes embedded between power and ground planes and multiple voltage supplies within the package substrate.
2. Description of Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
During manufacture of an integrated circuit (e.g., a microprocessor), signal lines formed upon the silicon substrate, which are to be connected to external devices, may be formed such that these lines terminate at flat metal contact regions called input/output (I/O) pads. Following manufacture, the integrated circuit may typically be secured within a protective semiconductor device package. Each I/O pad of the integrated circuit may be connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires may be used to connect the I/O pads of the chip to terminals of the device package. Some types of device packages have terminals called “pins” for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called “leads” for attachment to flat metal contact regions on an exposed surface of a PCB.
The I/O pads of the integrated circuit may be coupled to terminals of the device package configured to supply power from one voltage supply power plane to input/output drivers of the I/O. Integrated circuits are increasingly being designed to include input/output drivers requiring different voltage supplies on the same die. The location and number of input/output drivers requiring different voltage supplies may also vary in location and number depending upon the integrated circuit design. Therefore, each different integrated circuit design may require a custom designed package substrate. For example, each substrate would have to be laid out and designed thereby requiring engineering resources, increasing costs due to the separate tooling costs associated with each different substrate, and increasing the complexity of controlling the inventory of multiple different substrates. Therefore, current substrate design methodologies can not accommodate the different voltage supplies required by input/output drivers at acceptable costs.
As integrated circuit fabrication technology improves, manufacturers are able to integrate more and more circuits onto single silicon substrates. As the number of circuits on a single chip increases, however, the number of signal lines which need to be connected to external devices also increases. The corresponding numbers of required I/O pads and device package terminals increase as well as the complexities and costs of the device packages. Constraints of high volume PCB assembly operations place lower limits on the physical dimensions of and distances between device package terminals. As a result, the areas of peripheral-terminal device packages having hundreds of terminals are largely proportional to the number of terminals. These larger packages with fine-pitch leads are subject to mechanical damage during handling or testing. For example, mishandling may result in a loss of lead coplanarity, thereby adversely affecting PCB assembly yields. In addition, the lengths of signal lines from chip I/O pads to device package terminals increase with the number of terminals, and the high-frequency electrical performance of larger peripheral-terminal device packages suffer as a result.
Unlike more conventional peripheral-terminal device packages, grid array semiconductor device packages have terminals arranged in a two-dimensional array across the underside surface of the device package. As a result, the physical dimensions of grid array device packages having hundreds of terminals are much smaller than their peripheral-terminal counterparts. Such smaller packages are highly desirable in portable device applications such as laptop and palmtop computers and hand-held communications devices such as cellular telephones. In addition, the lengths of signal traces from the chip I/O pads to device package terminals are shorter, thus the high-frequency electrical performances of grid array device packages are typically better than those of corresponding peripheral-terminal device packages. Grid array device packages also allow the continued use of existing PCB assembly equipment developed for peripheral-terminal devices.
An increasingly popular type of grid array device package is the ball grid array (BGA) device package. A BGA device package includes a chip mounted upon a larger substrate substantially made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina (Al2O3), or aluminum nitride (AlN)). Many BGA device packages have die areas dimensioned to receive integrated circuit chips and use established wire bonding techniques to electrically connect the I/O pads of the chips to corresponding flat metal “signal bonding pads” adjacent to the die areas. During wire bonding, the I/O pads of the chip may be electrically connected to corresponding signal bonding pads by fine metal wires (i.e., bonding wires). The substrate may include one or more layers of signal lines (i.e., signal traces or interconnects) which may connect signal bonding pads to corresponding members of a set of ball pads arranged in a two-dimensional array across the underside surface of the device package. Solder balls may be attached to the ball pads, and function as device package terminals. The resulting solder balls on the underside of the BGA device package allow the device to be surface mounted to an ordinary PCB. During PCB assembly, the solder balls are placed in physical contact with corresponding ball pads of the PCB. The solder balls are then heated long enough for the solder to flow. When the solder cools, the ball pads on the underside of the package are electrically and mechanically coupled to ball pads of the PCB.
A BGA device package on a plastic carrier is known as a plastic ball grid array (PBGA) device. A PBGA, may include, for example, four conductive layers separated by three dielectric layers. The top conductive layer includes signal traces, the second conductive layer is a ground plane, the third conductive layer includes signal traces, and the bottom conductive layer is a power plane. A die is bonded to the top of this package. The die may be wirebonded to the substrate, which may be molded to cover and protect the die and the gold wire.
As dies become more dense and complex, the signal trace density of packages also increases. There are at least two problems associated with increases in signal trace density. First, the area on the signal trace layer may be insufficient for the required signal traces. Second, increasing signal trace density on a package may lead to increased cross talk between the signal traces and overall noise of the package. Therefore, current wire bonding layer methodologies may not accommodate the number of signal traces without violating current assembly or substrate design rules.